Semiconductor processing techniques continue to improve such that smaller devices can be fabricated. One example of a semiconductor processing technique is complementary metal-oxide semiconductor (“CMOS”) processing. As the devices formed using CMOS processing continue to be scaled down, tensile stresses attributed to layout-dependent effects (“LDEs”) impact the performance of devices formed using these advanced processing techniques.
For example, the LDEs impact the threshold voltage (“Vth”) of a device, the saturation current (“Idsat”) of a device, and the DC operation current (“Id”) of a device. Such device impacts affect the overall performance of a circuit regardless of whether a circuit is a radio frequency (“RF”) circuit, an analog or mixed signal circuit, or a digital circuit.